Static Timing Analysis

Project : battery_checker
Build Time : 11/30/13 20:19:43
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_Seq_1_intClock(FFB) ADC_SAR_Seq_1_intClock(FFB) 3.000 MHz 3.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
ADC_SAR_Seq_1_intClock CyHFCLK 3.000 MHz 3.000 MHz N/A
SCB_1_SCBCLK CyHFCLK 1.600 MHz 1.600 MHz N/A
Clock_1 CyHFCLK 2.000  Hz 2.000  Hz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
SCB_1_SCBCLK(FFB) SCB_1_SCBCLK(FFB) 1.600 MHz 1.600 MHz N/A