\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 29.216 | 34.228 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 23.556 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.126 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 29.216 | other | | | | .skew | 0.000 | 29.216 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 28.636 | 34.921 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 23.556 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.126 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 28.636 | other | | | | .skew | 0.000 | 28.636 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 28.506 | 35.080 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 23.556 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.126 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 28.506 | other | | | | .skew | 0.000 | 28.506 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 28.066 | 35.630 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 23.556 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.126 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 28.066 | other | | | | .skew | 0.000 | 28.066 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 27.786 | 35.989 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.126 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 22.696 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 27.786 | other | | | | .skew | 0.000 | 27.786 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 27.206 | 36.757 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.126 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 22.696 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 27.206 | other | | | | .skew | 0.000 | 27.206 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 27.076 | 36.933 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.126 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 22.696 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 27.076 | other | | | | .skew | 0.000 | 27.076 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 26.636 | 37.543 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.126 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 22.696 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 26.636 | other | | | | .skew | 0.000 | 26.636 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 26.356 | 37.942 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.696 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.266 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 26.356 | other | | | | .skew | 0.000 | 26.356 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 25.906 | 38.601 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 25.906 | other | | | | .skew | 0.000 | 25.906 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 25.776 | 38.796 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.696 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.266 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 25.776 | other | | | | .skew | 0.000 | 25.776 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 25.646 | 38.992 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.696 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.266 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 25.646 | other | | | | .skew | 0.000 | 25.646 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 25.345 | 39.456 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 19.685 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 20.255 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 25.345 | other | | | | .skew | 0.000 | 25.345 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 25.326 | 39.485 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 25.326 | other | | | | .skew | 0.000 | 25.326 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 25.206 | 39.673 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.696 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.266 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 25.206 | other | | | | .skew | 0.000 | 25.206 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 25.196 | 39.689 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 25.196 | other | | | | .skew | 0.000 | 25.196 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 24.765 | 40.380 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 19.685 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 20.255 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 24.765 | other | | | | .skew | 0.000 | 24.765 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 24.756 | 40.394 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.246 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 20.816 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 24.756 | other | | | | .skew | 0.000 | 24.756 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 24.635 | 40.593 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 19.685 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 20.255 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 24.635 | other | | | | .skew | 0.000 | 24.635 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 24.476 | 40.856 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 24.476 | other | | | | .skew | 0.000 | 24.476 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 24.195 | 41.331 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 19.685 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 20.255 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 24.195 | other | | | | .skew | 0.000 | 24.195 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 23.896 | 41.848 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 23.896 | other | | | | .skew | 0.000 | 23.896 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 23.766 | 42.077 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 23.766 | other | | | | .skew | 0.000 | 23.766 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 23.326 | 42.871 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 18.816 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.386 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 23.326 | other | | | | .skew | 0.000 | 23.326 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 23.046 | 43.392 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 23.046 | other | | | | .skew | 0.000 | 23.046 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 22.596 | 44.256 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_ov_msb | 12.000 | 22.596 | other | | | | .skew | 0.000 | 22.596 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 22.466 | 44.512 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 22.466 | other | | | | .skew | 0.000 | 22.466 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 22.336 | 44.771 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 22.336 | other | | | | .skew | 0.000 | 22.336 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 22.106 | 45.237 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a0 | 11.510 | 22.106 | other | | | | .skew | 0.000 | 22.106 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 22.035 | 45.382 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 22.035 | other | | | | .skew | 0.000 | 22.035 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 21.896 | 45.671 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.386 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 17.956 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 21.896 | other | | | | .skew | 0.000 | 21.896 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 21.886 | 45.691 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_co_msb | 11.290 | 21.886 | other | | | | .skew | 0.000 | 21.886 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 21.455 | 46.609 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 21.455 | other | | | | .skew | 0.000 | 21.455 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 21.446 | 46.629 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_d | 10.850 | 21.446 | other | | | | .skew | 0.000 | 21.446 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 21.325 | 46.893 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 21.325 | other | | | | .skew | 0.000 | 21.325 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 21.166 | 47.246 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_ov_msb | 12.000 | 21.166 | other | | | | .skew | 0.000 | 21.166 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 20.885 | 47.881 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 16.375 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 16.945 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 20.885 | other | | | | .skew | 0.000 | 20.885 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 20.676 | 48.365 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a0 | 11.510 | 20.676 | other | | | | .skew | 0.000 | 20.676 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 20.456 | 48.885 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_co_msb | 11.290 | 20.456 | other | | | | .skew | 0.000 | 20.456 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 20.016 | 49.960 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_d | 10.850 | 20.016 | other | | | | .skew | 0.000 | 20.016 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 19.736 | 50.669 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_ov_msb | 12.000 | 19.736 | other | | | | .skew | 0.000 | 19.736 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 19.246 | 51.959 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a0 | 11.510 | 19.246 | other | | | | .skew | 0.000 | 19.246 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 19.026 | 52.560 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_co_msb | 11.290 | 19.026 | other | | | | .skew | 0.000 | 19.026 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 18.725 | 53.405 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .sync_ov_msb | 12.000 | 18.725 | other | | | | .skew | 0.000 | 18.725 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 18.586 | 53.804 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_d | 10.850 | 18.586 | other | | | | .skew | 0.000 | 18.586 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 18.235 | 54.840 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .regd_a0 | 11.510 | 18.235 | other | | | | .skew | 0.000 | 18.235 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 18.015 | 55.509 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .sync_co_msb | 11.290 | 18.015 | other | | | | .skew | 0.000 | 18.015 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 17.575 | 56.899 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_d | 10.850 | 17.575 | other | | | | .skew | 0.000 | 17.575 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 17.487 | 57.186 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 3.124 | 9.834 | cell | U(3,2) | \Timer_1:TimerUDB:status_tc\ | .main_1 | .q | 3.350 | 13.184 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.313 | 15.497 | cell | U(2,2) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 17.487 | other | | | | .skew | 0.000 | 17.487 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 16.057 | 62.278 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 3.124 | 8.404 | cell | U(3,2) | \Timer_1:TimerUDB:status_tc\ | .main_1 | .q | 3.350 | 11.754 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.313 | 14.067 | cell | U(2,2) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 16.057 | other | | | | .skew | 0.000 | 16.057 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 16.016 | 62.438 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 10.596 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a1 | 5.420 | 16.016 | other | | | | .skew | 0.000 | 16.016 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 15.246 | 65.589 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.116 | 9.826 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_0 | .regd_a1 | 5.420 | 15.246 | other | | | | .skew | 0.000 | 15.246 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 14.627 | 68.367 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 3.124 | 6.974 | cell | U(3,2) | \Timer_1:TimerUDB:status_tc\ | .main_1 | .q | 3.350 | 10.324 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.313 | 12.637 | cell | U(2,2) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 14.627 | other | | | | .skew | 0.000 | 14.627 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 14.586 | 68.559 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 9.166 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a1 | 5.420 | 14.586 | other | | | | .skew | 0.000 | 14.586 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 14.444 | 69.235 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 2.314 | 9.024 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_0 | .regd_a1 | 5.420 | 14.444 | other | | | | .skew | 0.000 | 14.444 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 13.816 | 72.378 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.116 | 8.396 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_0 | .regd_a1 | 5.420 | 13.816 | other | | | | .skew | 0.000 | 13.816 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 13.500 | 74.074 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .main_0 | 3.267 | 5.847 | cell | U(3,2) | \Timer_1:TimerUDB:status_tc\ | .main_0 | .q | 3.350 | 9.197 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.313 | 11.510 | cell | U(2,2) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 13.500 | other | | | | .skew | 0.000 | 13.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | Net_34:macrocell.mc_d | 13.344 | 74.940 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 3.124 | 9.834 | cell | U(3,2) | Net_34 | .main_1 | .mc_d | 3.510 | 13.344 | other | | | | .skew | 0.000 | 13.344 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 13.156 | 76.011 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.886 | 7.736 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a1 | 5.420 | 13.156 | other | | | | .skew | 0.000 | 13.156 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 13.014 | 76.843 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 2.314 | 7.594 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_0 | .regd_a1 | 5.420 | 13.014 | other | | | | .skew | 0.000 | 13.014 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 12.386 | 80.734 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.116 | 6.966 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_0 | .regd_a1 | 5.420 | 12.386 | other | | | | .skew | 0.000 | 12.386 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 12.145 | 82.339 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.145 | 6.725 | cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .regd_a1 | 5.420 | 12.145 | other | | | | .skew | 0.000 | 12.145 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | Net_34:macrocell.mc_d | 11.914 | 83.935 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 3.124 | 8.404 | cell | U(3,2) | Net_34 | .main_1 | .mc_d | 3.510 | 11.914 | other | | | | .skew | 0.000 | 11.914 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 11.584 | 86.329 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 2.314 | 6.164 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_0 | .regd_a1 | 5.420 | 11.584 | other | | | | .skew | 0.000 | 11.584 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 11.288 | 88.588 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 3.288 | 5.868 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_1 | .regd_a1 | 5.420 | 11.288 | other | | | | .skew | 0.000 | 11.288 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 11.268 | 88.746 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 3.268 | 5.848 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_1 | .regd_a1 | 5.420 | 11.268 | other | | | | .skew | 0.000 | 11.268 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | Net_34:macrocell.mc_d | 10.484 | 95.384 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 3.124 | 6.974 | cell | U(3,2) | Net_34 | .main_1 | .mc_d | 3.510 | 10.484 | other | | | | .skew | 0.000 | 10.484 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 9.820 | 101.833 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .cl1_ch | 0.960 | 6.430 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 7.000 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 9.820 | other | | | | .skew | 0.000 | 9.820 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 9.820 | 101.833 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .cl1_ch | 0.960 | 6.430 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 7.000 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 9.820 | other | | | | .skew | 0.000 | 9.820 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | Net_34:macrocell.mc_d | 9.357 | 106.872 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .main_0 | 3.267 | 5.847 | cell | U(3,2) | Net_34 | .main_0 | .mc_d | 3.510 | 9.357 | other | | | | .skew | 0.000 | 9.357 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 9.000 | 111.111 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .cl0_ch | 0.930 | 5.640 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 6.210 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 9.000 | other | | | | .skew | 0.000 | 9.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 9.000 | 111.111 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .cl0_ch | 0.930 | 5.640 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 6.210 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 9.000 | other | | | | .skew | 0.000 | 9.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 8.440 | 118.483 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .ce1_ch | 0.960 | 5.050 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 5.620 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 8.440 | other | | | | .skew | 0.000 | 8.440 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 8.440 | 118.483 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .ce1_ch | 0.960 | 5.050 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 5.620 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 8.440 | other | | | | .skew | 0.000 | 8.440 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 8.400 | 119.048 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .ce0_ch | 0.930 | 5.040 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 5.610 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 8.400 | other | | | | .skew | 0.000 | 8.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 8.400 | 119.048 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .ce0_ch | 0.930 | 5.040 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 5.610 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 8.400 | other | | | | .skew | 0.000 | 8.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff0 | 7.420 | 134.771 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff0_ch | 2.730 | 2.730 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0_ch | .ff0i | 0.570 | 3.300 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0i | .ff0_ch | 0.860 | 4.160 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0_ch | .ff0i | 0.570 | 4.730 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0i | .sync_ff0 | 2.690 | 7.420 | other | | | | .skew | 0.000 | 7.420 |
|
Net_34:macrocell.mc_q | isr_1:interrupt.interrupt | 7.055 | | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | Net_34 | .pld0_clk | .q | 1.250 | 1.250 | route | | Net_34 | .q | .interrupt | 5.805 | 7.055 | other | | | | .skew | 0.000 | 7.055 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z0 | 7.010 | 142.653 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .sync_z0 | 2.690 | 7.010 | other | | | | .skew | 0.000 | 7.010 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z1 | 6.980 | 143.266 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z1_ch | 2.290 | 2.290 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1_ch | .z1i | 0.570 | 2.860 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1i | .z1_ch | 0.860 | 3.720 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1_ch | .z1i | 0.570 | 4.290 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1i | .sync_z1 | 2.690 | 6.980 | other | | | | .skew | 0.000 | 6.980 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff1 | 6.860 | 145.773 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff1_ch | 2.170 | 2.170 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1_ch | .ff1i | 0.570 | 2.740 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1i | .ff1_ch | 0.860 | 3.600 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1_ch | .ff1i | 0.570 | 4.170 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1i | .sync_ff1 | 2.690 | 6.860 | other | | | | .skew | 0.000 | 6.860 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff0 | 5.990 | 166.945 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ff0_ch | 2.730 | 2.730 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0_ch | .ff0i | 0.570 | 3.300 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0i | .sync_ff0 | 2.690 | 5.990 | other | | | | .skew | 0.000 | 5.990 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff0 | 5.990 | 166.945 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff0_ch | 2.730 | 2.730 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0_ch | .ff0i | 0.570 | 3.300 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0i | .sync_ff0 | 2.690 | 5.990 | other | | | | .skew | 0.000 | 5.990 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z0 | 5.580 | 179.211 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .sync_z0 | 2.690 | 5.580 | other | | | | .skew | 0.000 | 5.580 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z0 | 5.580 | 179.211 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .sync_z0 | 2.690 | 5.580 | other | | | | .skew | 0.000 | 5.580 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z1 | 5.550 | 180.180 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z1_ch | 2.290 | 2.290 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1_ch | .z1i | 0.570 | 2.860 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1i | .sync_z1 | 2.690 | 5.550 | other | | | | .skew | 0.000 | 5.550 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z1 | 5.550 | 180.180 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z1_ch | 2.290 | 2.290 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1_ch | .z1i | 0.570 | 2.860 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1i | .sync_z1 | 2.690 | 5.550 | other | | | | .skew | 0.000 | 5.550 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff1 | 5.430 | 184.162 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ff1_ch | 2.170 | 2.170 | other | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1_ch | .ff1i | 0.570 | 2.740 | cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1i | .sync_ff1 | 2.690 | 5.430 | other | | | | .skew | 0.000 | 5.430 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff1 | 5.430 | 184.162 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff1_ch | 2.170 | 2.170 | other | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1_ch | .ff1i | 0.570 | 2.740 | cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1i | .sync_ff1 | 2.690 | 5.430 | other | | | | .skew | 0.000 | 5.430 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cmsb | 5.000 | 200.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cmsb | 5.000 | 5.000 | other | | | | .skew | 0.000 | 5.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cmsb | 5.000 | 200.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cmsb | 5.000 | 5.000 | other | | | | .skew | 0.000 | 5.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cmsb | 5.000 | 200.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cmsb | 5.000 | 5.000 | other | | | | .skew | 0.000 | 5.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff0 | 4.560 | 219.298 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ff0 | 4.560 | 4.560 | other | | | | .skew | 0.000 | 4.560 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ff0 | 4.560 | 219.298 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ff0 | 4.560 | 4.560 | other | | | | .skew | 0.000 | 4.560 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff0 | 4.560 | 219.298 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ff0 | 4.560 | 4.560 | other | | | | .skew | 0.000 | 4.560 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z0 | 4.150 | 240.964 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_z0 | 4.150 | 4.150 | other | | | | .skew | 0.000 | 4.150 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_z0 | 4.150 | 240.964 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_z0 | 4.150 | 4.150 | other | | | | .skew | 0.000 | 4.150 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z0 | 4.150 | 240.964 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_z0 | 4.150 | 4.150 | other | | | | .skew | 0.000 | 4.150 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_z1 | 4.120 | 242.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_z1 | 4.120 | 4.120 | other | | | | .skew | 0.000 | 4.120 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z1 | 4.120 | 242.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_z1 | 4.120 | 4.120 | other | | | | .skew | 0.000 | 4.120 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z1 | 4.120 | 242.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_z1 | 4.120 | 4.120 | other | | | | .skew | 0.000 | 4.120 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff1 | 4.000 | 250.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,2) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ff1 | 4.000 | 4.000 | other | | | | .skew | 0.000 | 4.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff1 | 4.000 | 250.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,2) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ff1 | 4.000 | 4.000 | other | | | | .skew | 0.000 | 4.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ff1 | 4.000 | 250.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,3) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ff1 | 4.000 | 4.000 | other | | | | .skew | 0.000 | 4.000 |
|