\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 29.818 | 33.537 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 24.158 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.728 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 29.818 | other | | | | .skew | 0.000 | 29.818 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 29.238 | 34.202 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 24.158 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.728 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 29.238 | other | | | | .skew | 0.000 | 29.238 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 29.108 | 34.355 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 24.158 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.728 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 29.108 | other | | | | .skew | 0.000 | 29.108 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 28.668 | 34.882 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 24.158 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 24.728 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 28.668 | other | | | | .skew | 0.000 | 28.668 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 28.388 | 35.226 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.728 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 23.298 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 28.388 | other | | | | .skew | 0.000 | 28.388 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 27.808 | 35.961 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.728 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 23.298 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 27.808 | other | | | | .skew | 0.000 | 27.808 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 27.678 | 36.130 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.728 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 23.298 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 27.678 | other | | | | .skew | 0.000 | 27.678 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 27.238 | 36.713 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 22.728 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 23.298 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 27.238 | other | | | | .skew | 0.000 | 27.238 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 26.958 | 37.095 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 21.298 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.868 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 26.958 | other | | | | .skew | 0.000 | 26.958 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ov_msb | 26.552 | 37.662 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.892 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.462 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_ov_msb | 5.090 | 26.552 | other | | | | .skew | 0.000 | 26.552 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 26.508 | 37.725 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 26.508 | other | | | | .skew | 0.000 | 26.508 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 26.378 | 37.910 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 21.298 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.868 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 26.378 | other | | | | .skew | 0.000 | 26.378 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 26.248 | 38.098 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 21.298 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.868 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 26.248 | other | | | | .skew | 0.000 | 26.248 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a0 | 25.972 | 38.503 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.892 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.462 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .regd_a0 | 4.510 | 25.972 | other | | | | .skew | 0.000 | 25.972 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 25.928 | 38.568 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 25.928 | other | | | | .skew | 0.000 | 25.928 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_co_msb | 25.842 | 38.697 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.892 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.462 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .sync_co_msb | 4.380 | 25.842 | other | | | | .skew | 0.000 | 25.842 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 25.808 | 38.748 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 21.298 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.868 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 25.808 | other | | | | .skew | 0.000 | 25.808 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 25.798 | 38.763 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 25.798 | other | | | | .skew | 0.000 | 25.798 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.co_d | 25.402 | 39.367 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_ch | 2.740 | 20.892 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .co_ch | .ci | 0.570 | 21.462 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ci | .co_d | 3.940 | 25.402 | other | | | | .skew | 0.000 | 25.402 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 25.358 | 39.435 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 20.848 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 21.418 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 25.358 | other | | | | .skew | 0.000 | 25.358 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 25.078 | 39.876 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 25.078 | other | | | | .skew | 0.000 | 25.078 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 24.498 | 40.820 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 24.498 | other | | | | .skew | 0.000 | 24.498 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 24.368 | 41.038 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 24.368 | other | | | | .skew | 0.000 | 24.368 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 23.928 | 41.792 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 19.418 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 19.988 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 23.928 | other | | | | .skew | 0.000 | 23.928 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 23.648 | 42.287 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 23.648 | other | | | | .skew | 0.000 | 23.648 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ov_msb | 23.242 | 43.025 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_ov_msb | 5.090 | 23.242 | other | | | | .skew | 0.000 | 23.242 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 23.198 | 43.107 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_ov_msb | 12.000 | 23.198 | other | | | | .skew | 0.000 | 23.198 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 23.068 | 43.350 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 23.068 | other | | | | .skew | 0.000 | 23.068 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 22.938 | 43.596 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 22.938 | other | | | | .skew | 0.000 | 22.938 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 22.708 | 44.037 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a0 | 11.510 | 22.708 | other | | | | .skew | 0.000 | 22.708 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a0 | 22.662 | 44.126 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .regd_a0 | 4.510 | 22.662 | other | | | | .skew | 0.000 | 22.662 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_co_msb | 22.532 | 44.381 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .sync_co_msb | 4.380 | 22.532 | other | | | | .skew | 0.000 | 22.532 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 22.498 | 44.448 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_ch | 9.650 | 17.988 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.558 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 22.498 | other | | | | .skew | 0.000 | 22.498 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 22.488 | 44.468 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_co_msb | 11.290 | 22.488 | other | | | | .skew | 0.000 | 22.488 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.co_d | 22.092 | 45.265 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_ch | 9.650 | 17.582 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .co_ch | .ci | 0.570 | 18.152 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ci | .co_d | 3.940 | 22.092 | other | | | | .skew | 0.000 | 22.092 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 22.048 | 45.356 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_d | 10.850 | 22.048 | other | | | | .skew | 0.000 | 22.048 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 21.768 | 45.939 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_ov_msb | 12.000 | 21.768 | other | | | | .skew | 0.000 | 21.768 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 21.278 | 46.997 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a0 | 11.510 | 21.278 | other | | | | .skew | 0.000 | 21.278 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 21.058 | 47.488 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_co_msb | 11.290 | 21.058 | other | | | | .skew | 0.000 | 21.058 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 20.618 | 48.501 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_d | 10.850 | 20.618 | other | | | | .skew | 0.000 | 20.618 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 20.338 | 49.169 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_ov_msb | 12.000 | 20.338 | other | | | | .skew | 0.000 | 20.338 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ov_msb | 19.932 | 50.170 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .sync_ov_msb | 12.000 | 19.932 | other | | | | .skew | 0.000 | 19.932 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 19.848 | 50.383 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a0 | 11.510 | 19.848 | other | | | | .skew | 0.000 | 19.848 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 19.628 | 50.948 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .sync_co_msb | 11.290 | 19.628 | other | | | | .skew | 0.000 | 19.628 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a0 | 19.442 | 51.435 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .regd_a0 | 11.510 | 19.442 | other | | | | .skew | 0.000 | 19.442 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_co_msb | 19.222 | 52.023 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .sync_co_msb | 11.290 | 19.222 | other | | | | .skew | 0.000 | 19.222 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 19.188 | 52.116 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .co_d | 10.850 | 19.188 | other | | | | .skew | 0.000 | 19.188 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.co_d | 18.782 | 53.242 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .co_d | 10.850 | 18.782 | other | | | | .skew | 0.000 | 18.782 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 16.708 | 59.852 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 2.332 | 9.042 | cell | U(2,4) | \Timer_1:TimerUDB:status_tc\ | .main_1 | .q | 3.350 | 12.392 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.325 | 14.718 | cell | U(2,4) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 16.708 | other | | | | .skew | 0.000 | 16.708 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 16.618 | 60.176 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 11.198 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a1 | 5.420 | 16.618 | other | | | | .skew | 0.000 | 16.618 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 15.290 | 65.401 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.160 | 9.870 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_0 | .regd_a1 | 5.420 | 15.290 | other | | | | .skew | 0.000 | 15.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 15.278 | 65.455 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 2.332 | 7.612 | cell | U(2,4) | \Timer_1:TimerUDB:status_tc\ | .main_1 | .q | 3.350 | 10.962 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.325 | 13.288 | cell | U(2,4) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 15.278 | other | | | | .skew | 0.000 | 15.278 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 15.188 | 65.842 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 9.768 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a1 | 5.420 | 15.188 | other | | | | .skew | 0.000 | 15.188 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 14.849 | 67.344 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .main_0 | 4.604 | 7.184 | cell | U(2,4) | \Timer_1:TimerUDB:status_tc\ | .main_0 | .q | 3.350 | 10.534 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.325 | 12.859 | cell | U(2,4) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 14.849 | other | | | | .skew | 0.000 | 14.849 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 14.431 | 69.297 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 2.301 | 9.011 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_0 | .regd_a1 | 5.420 | 14.431 | other | | | | .skew | 0.000 | 14.431 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 13.860 | 72.149 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.160 | 8.440 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_0 | .regd_a1 | 5.420 | 13.860 | other | | | | .skew | 0.000 | 13.860 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:rstSts:stsreg\:statusicell.regd0 | 13.848 | 72.214 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 2.332 | 6.182 | cell | U(2,4) | \Timer_1:TimerUDB:status_tc\ | .main_1 | .q | 3.350 | 9.532 | route | | \Timer_1:TimerUDB:status_tc\ | .q | .status_0 | 2.325 | 11.858 | cell | U(2,4) | \Timer_1:TimerUDB:rstSts:stsreg\ | .status_0 | .regd0 | 1.990 | 13.848 | other | | | | .skew | 0.000 | 13.848 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 13.758 | 72.685 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 4.488 | 8.338 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_0 | .regd_a1 | 5.420 | 13.758 | other | | | | .skew | 0.000 | 13.758 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regd_a1 | 13.352 | 74.894 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 5.352 | 7.932 | cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .cs_addr_1 | .regd_a1 | 5.420 | 13.352 | other | | | | .skew | 0.000 | 13.352 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 13.001 | 76.919 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 2.301 | 7.581 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_0 | .regd_a1 | 5.420 | 13.001 | other | | | | .skew | 0.000 | 13.001 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 12.637 | 79.132 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.637 | 7.217 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_1 | .regd_a1 | 5.420 | 12.637 | other | | | | .skew | 0.000 | 12.637 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 12.621 | 79.231 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .cs_addr_1 | 4.621 | 7.201 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_1 | .regd_a1 | 5.420 | 12.621 | other | | | | .skew | 0.000 | 12.621 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | Net_55:macrocell.mc_d | 12.552 | 79.666 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 6.710 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 2.332 | 9.042 | cell | U(2,4) | Net_55 | .main_1 | .mc_d | 3.510 | 12.552 | other | | | | .skew | 0.000 | 12.552 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regd_a1 | 12.430 | 80.449 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 3.160 | 7.010 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cs_addr_0 | .regd_a1 | 5.420 | 12.430 | other | | | | .skew | 0.000 | 12.430 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regd_a1 | 11.571 | 86.425 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .cs_addr_0 | 2.301 | 6.151 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cs_addr_0 | .regd_a1 | 5.420 | 11.571 | other | | | | .skew | 0.000 | 11.571 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | Net_55:macrocell.mc_d | 11.122 | 89.909 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .z0_comb | 2.390 | 5.280 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 2.332 | 7.612 | cell | U(2,4) | Net_55 | .main_1 | .mc_d | 3.510 | 11.122 | other | | | | .skew | 0.000 | 11.122 |
|
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\:controlcell.control_7 | Net_55:macrocell.mc_d | 10.694 | 93.513 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
other | U(3,2) | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | .sc_clk | .control_7 | 2.580 | 2.580 | route | | \Timer_1:TimerUDB:control_7\ | .control_7 | .main_0 | 4.604 | 7.184 | cell | U(2,4) | Net_55 | .main_0 | .mc_d | 3.510 | 10.694 | other | | | | .skew | 0.000 | 10.694 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 9.820 | 101.833 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .cl1_ch | 0.960 | 6.430 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 7.000 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 9.820 | other | | | | .skew | 0.000 | 9.820 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 9.820 | 101.833 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .cl1_ch | 0.960 | 6.430 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 7.000 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 9.820 | other | | | | .skew | 0.000 | 9.820 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | Net_55:macrocell.mc_d | 9.692 | 103.174 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .z0_comb | 3.850 | 3.850 | route | | \Timer_1:TimerUDB:per_zero\ | .z0_comb | .main_1 | 2.332 | 6.182 | cell | U(2,4) | Net_55 | .main_1 | .mc_d | 3.510 | 9.692 | other | | | | .skew | 0.000 | 9.692 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 9.000 | 111.111 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .cl0_ch | 0.930 | 5.640 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 6.210 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 9.000 | other | | | | .skew | 0.000 | 9.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 9.000 | 111.111 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .cl0_ch | 0.930 | 5.640 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 6.210 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 9.000 | other | | | | .skew | 0.000 | 9.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 8.440 | 118.483 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .ce1_ch | 0.960 | 5.050 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 5.620 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 8.440 | other | | | | .skew | 0.000 | 8.440 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 8.440 | 118.483 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .ce1_ch | 0.960 | 5.050 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 5.620 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 8.440 | other | | | | .skew | 0.000 | 8.440 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 8.400 | 119.048 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .ce0_ch | 0.930 | 5.040 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 5.610 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 8.400 | other | | | | .skew | 0.000 | 8.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 8.400 | 119.048 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .ce0_ch | 0.930 | 5.040 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 5.610 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 8.400 | other | | | | .skew | 0.000 | 8.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 8.290 | 120.627 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl1_ch | 4.900 | 4.900 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1_ch | .cl1i | 0.570 | 5.470 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl1i | .sync_cl1 | 2.820 | 8.290 | other | | | | .skew | 0.000 | 8.290 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 7.500 | 133.333 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .cl0_ch | 4.140 | 4.140 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0_ch | .cl0i | 0.570 | 4.710 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .cl0i | .sync_cl0 | 2.790 | 7.500 | other | | | | .skew | 0.000 | 7.500 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff0 | 7.420 | 134.771 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff0_ch | 2.730 | 2.730 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0_ch | .ff0i | 0.570 | 3.300 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0i | .ff0_ch | 0.860 | 4.160 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0_ch | .ff0i | 0.570 | 4.730 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0i | .sync_ff0 | 2.690 | 7.420 | other | | | | .skew | 0.000 | 7.420 |
|
Net_55:macrocell.mc_q | irt_timer1:interrupt.interrupt | 7.135 | | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | Net_55 | .pld0_clk | .q | 1.250 | 1.250 | route | | Net_55 | .q | .interrupt | 5.885 | 7.135 | other | | | | .skew | 0.000 | 7.135 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z0 | 7.010 | 142.653 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .z0_ch | 0.860 | 3.750 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 4.320 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .sync_z0 | 2.690 | 7.010 | other | | | | .skew | 0.000 | 7.010 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z1 | 6.980 | 143.266 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z1_ch | 2.290 | 2.290 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1_ch | .z1i | 0.570 | 2.860 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1i | .z1_ch | 0.860 | 3.720 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1_ch | .z1i | 0.570 | 4.290 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1i | .sync_z1 | 2.690 | 6.980 | other | | | | .skew | 0.000 | 6.980 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 6.910 | 144.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce1_ch | 3.520 | 3.520 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1_ch | .ce1i | 0.570 | 4.090 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce1i | .sync_ce1 | 2.820 | 6.910 | other | | | | .skew | 0.000 | 6.910 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 6.900 | 144.928 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ce0_ch | 3.540 | 3.540 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0_ch | .ce0i | 0.570 | 4.110 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ce0i | .sync_ce0 | 2.790 | 6.900 | other | | | | .skew | 0.000 | 6.900 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff1 | 6.860 | 145.773 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff1_ch | 2.170 | 2.170 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1_ch | .ff1i | 0.570 | 2.740 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1i | .ff1_ch | 0.860 | 3.600 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1_ch | .ff1i | 0.570 | 4.170 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1i | .sync_ff1 | 2.690 | 6.860 | other | | | | .skew | 0.000 | 6.860 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl1 | 6.760 | 147.929 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl1 | 6.760 | 6.760 | other | | | | .skew | 0.000 | 6.760 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cl0 | 6.000 | 166.667 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cl0 | 6.000 | 6.000 | other | | | | .skew | 0.000 | 6.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff0 | 5.990 | 166.945 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ff0_ch | 2.730 | 2.730 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0_ch | .ff0i | 0.570 | 3.300 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff0i | .sync_ff0 | 2.690 | 5.990 | other | | | | .skew | 0.000 | 5.990 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff0 | 5.990 | 166.945 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff0_ch | 2.730 | 2.730 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0_ch | .ff0i | 0.570 | 3.300 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff0i | .sync_ff0 | 2.690 | 5.990 | other | | | | .skew | 0.000 | 5.990 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z0 | 5.580 | 179.211 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z0i | .sync_z0 | 2.690 | 5.580 | other | | | | .skew | 0.000 | 5.580 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z0 | 5.580 | 179.211 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z0_ch | 2.320 | 2.320 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0_ch | .z0i | 0.570 | 2.890 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z0i | .sync_z0 | 2.690 | 5.580 | other | | | | .skew | 0.000 | 5.580 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z1 | 5.550 | 180.180 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .z1_ch | 2.290 | 2.290 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1_ch | .z1i | 0.570 | 2.860 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .z1i | .sync_z1 | 2.690 | 5.550 | other | | | | .skew | 0.000 | 5.550 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z1 | 5.550 | 180.180 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .z1_ch | 2.290 | 2.290 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1_ch | .z1i | 0.570 | 2.860 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .z1i | .sync_z1 | 2.690 | 5.550 | other | | | | .skew | 0.000 | 5.550 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff1 | 5.430 | 184.162 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .ff1_ch | 2.170 | 2.170 | other | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1_ch | .ff1i | 0.570 | 2.740 | cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .ff1i | .sync_ff1 | 2.690 | 5.430 | other | | | | .skew | 0.000 | 5.430 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff1 | 5.430 | 184.162 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .ff1_ch | 2.170 | 2.170 | other | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1_ch | .ff1i | 0.570 | 2.740 | cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .ff1i | .sync_ff1 | 2.690 | 5.430 | other | | | | .skew | 0.000 | 5.430 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce0 | 5.400 | 185.185 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce0 | 5.400 | 5.400 | other | | | | .skew | 0.000 | 5.400 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_d1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ce1 | 5.380 | 185.874 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ce1 | 5.380 | 5.380 | other | | | | .skew | 0.000 | 5.380 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_cmsb | 5.000 | 200.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_cmsb | 5.000 | 5.000 | other | | | | .skew | 0.000 | 5.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_cmsb | 5.000 | 200.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_cmsb | 5.000 | 5.000 | other | | | | .skew | 0.000 | 5.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_cmsb | 5.000 | 200.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_cmsb | 5.000 | 5.000 | other | | | | .skew | 0.000 | 5.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff0 | 4.560 | 219.298 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ff0 | 4.560 | 4.560 | other | | | | .skew | 0.000 | 4.560 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ff0 | 4.560 | 219.298 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ff0 | 4.560 | 4.560 | other | | | | .skew | 0.000 | 4.560 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff0 | 4.560 | 219.298 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ff0 | 4.560 | 4.560 | other | | | | .skew | 0.000 | 4.560 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z0 | 4.150 | 240.964 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_z0 | 4.150 | 4.150 | other | | | | .skew | 0.000 | 4.150 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_z0 | 4.150 | 240.964 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_z0 | 4.150 | 4.150 | other | | | | .skew | 0.000 | 4.150 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a0 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z0 | 4.150 | 240.964 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_z0 | 4.150 | 4.150 | other | | | | .skew | 0.000 | 4.150 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_z1 | 4.120 | 242.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_z1 | 4.120 | 4.120 | other | | | | .skew | 0.000 | 4.120 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_z1 | 4.120 | 242.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_z1 | 4.120 | 4.120 | other | | | | .skew | 0.000 | 4.120 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_z1 | 4.120 | 242.718 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_z1 | 4.120 | 4.120 | other | | | | .skew | 0.000 | 4.120 |
|
\Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u1\:datapathcell.sync_ff1 | 4.000 | 250.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,4) | \Timer_1:TimerUDB:sT24:timerdp:u1\ | .dp_clk | .sync_ff1 | 4.000 | 4.000 | other | | | | .skew | 0.000 | 4.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u2\:datapathcell.sync_ff1 | 4.000 | 250.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(2,4) | \Timer_1:TimerUDB:sT24:timerdp:u2\ | .dp_clk | .sync_ff1 | 4.000 | 4.000 | other | | | | .skew | 0.000 | 4.000 |
|
\Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.regq_a1 | \Timer_1:TimerUDB:sT24:timerdp:u0\:datapathcell.sync_ff1 | 4.000 | 250.000 MHz | 24.000 MHz | |
Type | Location | Instance/Net | Source | Destination | Delay (ns) | Total (ns) |
---|
cell | U(3,5) | \Timer_1:TimerUDB:sT24:timerdp:u0\ | .dp_clk | .sync_ff1 | 4.000 | 4.000 | other | | | | .skew | 0.000 | 4.000 |
|