Synthesis and Ngdbuild  Report
#Build: Synplify for Lattice 9.6L2, Build 066R, Oct 28 2008
#install: E:\ISPTOOLS7_2_STRT\synpbase
#OS:  6.1
#Hostname: WENDY

#Implementation: ramen_timer_lattice

#Wed Jun 03 23:59:09 2009

$ Start of Compile
#Wed Jun 03 23:59:09 2009

Synplicity VHDL Compiler, version 1.0, Build 020R, built Nov  5 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@N: CD720 :"E:\ISPTOOLS7_2_STRT\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
Top entity isn't set yet!
VHDL syntax check successful!
@N: CD630 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":30:7:30:17|Synthesizing work.ramen_timer.behavioral 
@W: CD604 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":174:8:174:21|OTHERS clause is not synthesized 
@W: CD604 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":194:8:194:21|OTHERS clause is not synthesized 
@W: CD604 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":214:8:214:21|OTHERS clause is not synthesized 
@W: CD604 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":234:8:234:21|OTHERS clause is not synthesized 
@N: CD630 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\counter10.vhd":30:7:30:15|Synthesizing work.counter10.behavioral 
@W: CG296 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\counter10.vhd":47:1:47:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\counter10.vhd":79:15:79:17|Referenced variable dat is not in sensitivity list
Post processing for work.counter10.behavioral
Post processing for work.ramen_timer.behavioral
@W: CL240 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":40:11:40:14|BEEP is not assigned a value (floating) - a simulation mismatch is possible 
@W: CL169 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Pruning Register setnum4(3 downto 0)  
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit SEG7_1(7) is always 1, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit SEG7_3(7) is always 1, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit SEG7_4(7) is always 1, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit setnum1(2) is always 0, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit setnum1(3) is always 0, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit setnum2(1) is always 0, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit setnum3(0) is always 0, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit setnum3(1) is always 0, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit setnum3(2) is always 0, optimizing ...
@W: CL189 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Register bit setnum3(3) is always 0, optimizing ...
@W: CL171 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Pruning Register bit <3> of setnum1(3 downto 0)  
@W: CL171 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Pruning Register bit <2> of setnum1(3 downto 0)  
@W: CL171 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Pruning Register bit <1> of setnum2(3 downto 0)  
@W: CL171 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Pruning Register bit <7> of SEG7_1(7 downto 0)  
@W: CL171 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Pruning Register bit <7> of SEG7_3(7 downto 0)  
@W: CL171 :"D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":112:4:112:5|Pruning Register bit <7> of SEG7_4(7 downto 0)  
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jun 03 23:59:10 2009

###########################################################]
Synplicity Generic Technology Mapper, Version 9.4.2, Build 078R, Built Dec 17 2008 10:08:25
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.6L2
@W: BN246 |Failed to find top level module 'work.ramen_timer' as specified in project file
@N: MF249 |Running in 32-bit mode.

Automatic dissolve at startup in view:work.ramen_timer(behavioral) of KETA1(counter10_KETA1)
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":217:6:217:9|Rom SEG7_4_1_1[6:0] mapped in logic.
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":197:6:197:9|Rom SEG7_3_1_1[6:0] mapped in logic.
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":177:6:177:9|Rom SEG7_2_1[6:0] mapped in logic.
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":157:6:157:9|Rom SEG7_1_17[6:0] mapped in logic.
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":217:6:217:9|Rom SEG7_4_1_1[6:0] mapped in logic.
@N: MO106 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":217:6:217:9|Found ROM, 'SEG7_4_1_1[6:0]', 16 words by 7 bits 
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":197:6:197:9|Rom SEG7_3_1_1[6:0] mapped in logic.
@N: MO106 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":197:6:197:9|Found ROM, 'SEG7_3_1_1[6:0]', 16 words by 7 bits 
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":177:6:177:9|Rom SEG7_2_1[6:0] mapped in logic.
@N: MO106 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":177:6:177:9|Found ROM, 'SEG7_2_1[6:0]', 16 words by 7 bits 
@N: FA239 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":157:6:157:9|Rom SEG7_1_17[6:0] mapped in logic.
@N: MO106 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.vhd":157:6:157:9|Found ROM, 'SEG7_1_17[6:0]', 16 words by 7 bits 
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

Dissolving instances of view:work.counter10_KETA2(behavioral) before factorization cost=60, pathcnt=1
Dissolving instances of view:work.counter10_KETA3(behavioral) before factorization cost=60, pathcnt=1
Dissolving instances of view:work.counter10(behavioral) before factorization cost=56, pathcnt=1
@N: BN116 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\counter10.vhd":78:4:78:5|Removing sequential instance KETA4.CARRY of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 102MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 102MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 102MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 103MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.ramen_timer(behavioral):
No nets needed buffering.

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 103MB)

@W: BN132 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\counter10.vhd":78:4:78:5|Removing sequential instance KETA3.count_3_.Q.res_lat,  because it is equivalent to instance KETA2.count_3_.Q.res_lat
@W: BN132 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\counter10.vhd":78:4:78:5|Removing sequential instance KETA3.count_2_.Q.res_lat,  because it is equivalent to instance KETA2.count_2_.Q.res_lat
@W: BN132 :"d:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\counter10.vhd":78:4:78:5|Removing sequential instance KETA3.count_0_.Q.res_lat,  because it is equivalent to instance KETA2.count_0_.Q.res_lat
Warning: Found 5 combinational loops!
@W: BN137 :|Found combinational loop during mapping at net I_60.t2
1) instance work.ramen_timer(behavioral)-I_60.lat_r, output net "I_60.t2" in work.ramen_timer(behavioral)
    net        I_60.t2
    input  pin I_60.lat/I[0]
    instance   I_60.lat (cell or)
    output pin I_60.lat/OUT
    net        I_60.t1
    input  pin I_60.lat_r/I[1]
    instance   I_60.lat_r (cell and)
    output pin I_60.lat_r/OUT
    net        I_60.t2
@W: BN137 :|Found combinational loop during mapping at net I_59.t2
2) instance work.ramen_timer(behavioral)-I_59.lat_r, output net "I_59.t2" in work.ramen_timer(behavioral)
    net        I_59.t2
    input  pin I_59.lat/I[0]
    instance   I_59.lat (cell or)
    output pin I_59.lat/OUT
    net        I_59.t1
    input  pin I_59.lat_r/I[1]
    instance   I_59.lat_r (cell and)
    output pin I_59.lat_r/OUT
    net        I_59.t2
@W: BN137 :|Found combinational loop during mapping at net I_58.t2
3) instance work.ramen_timer(behavioral)-I_58.lat_r, output net "I_58.t2" in work.ramen_timer(behavioral)
    net        I_58.t2
    input  pin I_58.lat/I[0]
    instance   I_58.lat (cell or)
    output pin I_58.lat/OUT
    net        I_58.t1
    input  pin I_58.lat_r/I[1]
    instance   I_58.lat_r (cell and)
    output pin I_58.lat_r/OUT
    net        I_58.t2
@W: BN137 :|Found combinational loop during mapping at net I_57.t2
4) instance work.ramen_timer(behavioral)-I_57.lat_r, output net "I_57.t2" in work.ramen_timer(behavioral)
    net        I_57.t2
    input  pin I_57.lat/I[0]
    instance   I_57.lat (cell or)
    output pin I_57.lat/OUT
    net        I_57.t1
    input  pin I_57.lat_r/I[1]
    instance   I_57.lat_r (cell and)
    output pin I_57.lat_r/OUT
    net        I_57.t2
@W: BN137 :|Found combinational loop during mapping at net I_56.t2
5) instance work.ramen_timer(behavioral)-I_56.lat_r, output net "I_56.t2" in work.ramen_timer(behavioral)
    net        I_56.t2
    input  pin I_56.lat/I[0]
    instance   I_56.lat (cell or)
    output pin I_56.lat/OUT
    net        I_56.t1
    input  pin I_56.lat_r/I[1]
    instance   I_56.lat_r (cell and)
    output pin I_56.lat_r/OUT
    net        I_56.t2
End of loops
Found clock ramen_timer|CLK with period 5.00ns 
Found clock counter10_KETA2|CARRY_inferred_clock with period 5.00ns 
Found clock counter10_KETA3|CARRY_inferred_clock with period 5.00ns 
Found clock ramen_timer|count_signal_inferred_clock with period 5.00ns 
Found clock ramen_timer|KETA1.carry1_inferred_clock with period 5.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jun 03 23:59:11 2009
#


Top view:               ramen_timer
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: -0.281

                                            Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock                              Frequency     Frequency     Period        Period        Slack      Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------------------
counter10_KETA2|CARRY_inferred_clock        200.0 MHz     258.0 MHz     5.000         3.876         1.124      inferred     Inferred_clkgroup_3
counter10_KETA3|CARRY_inferred_clock        200.0 MHz     336.0 MHz     5.000         2.976         2.024      inferred     Inferred_clkgroup_4
ramen_timer|CLK                             200.0 MHz     189.4 MHz     5.000         5.281         -0.281     inferred     Inferred_clkgroup_1
ramen_timer|KETA1.carry1_inferred_clock     200.0 MHz     257.5 MHz     5.000         3.884         1.116      inferred     Inferred_clkgroup_2
ramen_timer|count_signal_inferred_clock     200.0 MHz     353.3 MHz     5.000         2.830         2.170      inferred     Inferred_clkgroup_0
===============================================================================================================================================





Clock Relationships
*******************

Clocks                                                                            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                 Ending                                   |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ramen_timer|count_signal_inferred_clock  ramen_timer|count_signal_inferred_clock  |  5.000       2.170   |  No paths    -      |  No paths    -      |  No paths    -    
ramen_timer|count_signal_inferred_clock  ramen_timer|CLK                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ramen_timer|CLK                          ramen_timer|CLK                          |  5.000       -0.281  |  No paths    -      |  No paths    -      |  No paths    -    
ramen_timer|CLK                          ramen_timer|KETA1.carry1_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ramen_timer|CLK                          counter10_KETA2|CARRY_inferred_clock     |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ramen_timer|CLK                          counter10_KETA3|CARRY_inferred_clock     |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ramen_timer|KETA1.carry1_inferred_clock  ramen_timer|CLK                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ramen_timer|KETA1.carry1_inferred_clock  ramen_timer|KETA1.carry1_inferred_clock  |  5.000       1.116   |  No paths    -      |  No paths    -      |  No paths    -    
counter10_KETA2|CARRY_inferred_clock     ramen_timer|CLK                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
counter10_KETA2|CARRY_inferred_clock     counter10_KETA2|CARRY_inferred_clock     |  5.000       1.124   |  No paths    -      |  No paths    -      |  No paths    -    
counter10_KETA3|CARRY_inferred_clock     ramen_timer|CLK                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
counter10_KETA3|CARRY_inferred_clock     counter10_KETA3|CARRY_inferred_clock     |  5.000       2.024   |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port     Starting            User           Arrival     Required          
Name     Reference           Constraint     Time        Time         Slack
         Clock                                                            
--------------------------------------------------------------------------
CLK      NA                  NA             NA          NA           NA   
SW1      System (rising)     NA             0.000       1.630             
SW2      System (rising)     NA             0.000       1.622             
SW3      System (rising)     NA             0.000       2.113             
SW4      System (rising)     NA             0.000       2.154             
==========================================================================


Output Ports: 

Port          Starting                     User           Arrival     Required          
Name          Reference                    Constraint     Time        Time         Slack
              Clock                                                                     
----------------------------------------------------------------------------------------
BEEP          NA                           NA             NA          NA           NA   
SEG7_1[0]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_1[1]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_1[2]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_1[3]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_1[4]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_1[5]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_1[6]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_1[7]     NA                           NA             NA          NA           NA   
SEG7_2[0]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_2[1]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_2[2]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_2[3]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_2[4]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_2[5]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_2[6]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_2[7]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[0]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[1]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[2]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[3]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[4]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[5]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[6]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_3[7]     NA                           NA             NA          NA           NA   
SEG7_4[0]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_4[1]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_4[2]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_4[3]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_4[4]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_4[5]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_4[6]     ramen_timer|CLK (rising)     NA             3.722       5.000             
SEG7_4[7]     NA                           NA             NA          NA           NA   
========================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lfxp2_5e-6

Register bits: 83 of 4752 (2%)
PIC Latch:       0
I/O cells:       38


Details:
CCU2B:          11
FD1P3AX:        2
FD1P3IX:        1
FD1S3AX:        20
FD1S3BX:        8
FD1S3DX:        19
FD1S3IX:        1
FD1S3JX:        3
GSR:            1
IB:             5
INV:            3
OB:             33
OFS1P3DX:       28
OFS1P3IX:       1
ORCALUT4:       102
PUR:            1
VHI:            1
VLO:            1
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 103MB)

Writing Analyst data base D:\home\rerofumi\works\komekame\pld\develop\ramen_timer_lattice\ramen_timer.srm
@N: MF203 |Set autoconstraint_io 
Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 103MB)

Writing EDIF Netlist and constraint files
Version 9.6L2
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:02s; Memory used current: 105MB peak: 106MB)

Writing Verilog Simulation files
Finished Writing Verilog Simulation files (Time elapsed 0h:00m:02s; Memory used current: 105MB peak: 106MB)

Writing VHDL Simulation files
Finished Writing VHDL Simulation files (Time elapsed 0h:00m:02s; Memory used current: 105MB peak: 106MB)

Mapper successful!
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Wed Jun 03 23:59:13 2009

###########################################################]



Generated from the file 'C:\Documents and Settings\rerofumi\My Documents\pld_develop\ramen_timer_lattice\ramen_timer.srf'