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Lattice TRACE Report - Setup, Version ispLever_v72_PROD_Build (44)
Thu Jun 04 01:27:34 2009

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2008 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 1 -gt -mapchkpnt 0 -o checkpnt.twr ramen_timer_map.ncd ramen_timer.prf 
Design file:     ramen_timer_map.ncd
Preference file: ramen_timer.prf
Device,speed:    LFXP2-5E,6
Report level:    verbose report, limited to 1 item per preference
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Preference Summary

  • FREQUENCY NET "CLK_c" 373.552000 MHz (604 errors)
  • 729 items scored, 604 timing errors detected. Warning: 30.580MHz is the maximum frequency for this preference.
  • FREQUENCY NET "count_signal_inferred_clock" 691.563000 MHz (15 errors)
  • 21 items scored, 15 timing errors detected. Warning: 366.166MHz is the maximum frequency for this preference.
  • FREQUENCY NET "carry3" 538.793000 MHz (48 errors)
  • 56 items scored, 48 timing errors detected. Warning: 237.079MHz is the maximum frequency for this preference.
  • FREQUENCY NET "carry2" 441.112000 MHz (133 errors)
  • 150 items scored, 133 timing errors detected. Warning: 166.639MHz is the maximum frequency for this preference.
  • FREQUENCY NET "carry1" 441.112000 MHz (135 errors)
  • 150 items scored, 135 timing errors detected. Warning: 166.639MHz is the maximum frequency for this preference. 5 potential circuit loops found in timing analysis. 5 potential circuit loops found in timing analysis. 5 potential circuit loops found in timing analysis. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "CLK_c" 373.552000 MHz ; 729 items scored, 604 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 4.610ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q KETA3/count_3__Q_res_reg_0 (from carry2 +) Destination: FF Data in count_signal (to CLK_c +) Delay: 4.944ns (26.6% logic, 73.4% route), 5 logic levels. Constraint Details: 4.944ns physical path delay SLICE_20 to SLICE_30 exceeds 0.411ns delay constraint less 0.077ns DIN_SET requirement (totaling 0.334ns) by 4.610ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.363 SLICE_20.CLK to SLICE_20.Q0 SLICE_20 (from carry2) ROUTE 1 e 0.907 SLICE_20.Q0 to SLICE_48.B0 KETA3/o1_1 CTOF_DEL --- 0.238 SLICE_48.B0 to SLICE_48.F0 SLICE_48 ROUTE 12 e 0.907 SLICE_48.F0 to SLICE_30.B1 display3_3 CTOF_DEL --- 0.238 SLICE_30.B1 to SLICE_30.F1 SLICE_30 ROUTE 1 e 0.907 SLICE_30.F1 to SLICE_50.D1 un12_timer_1_1 CTOF_DEL --- 0.238 SLICE_50.D1 to SLICE_50.F1 SLICE_50 ROUTE 1 e 0.907 SLICE_50.F1 to SLICE_30.C0 un12_timer_5 CTOF_DEL --- 0.238 SLICE_30.C0 to SLICE_30.F0 SLICE_30 ROUTE 1 e 0.001 SLICE_30.F0 to SLICE_30.DI0 un12_timer_i (to CLK_c) -------- 4.944 (26.6% logic, 73.4% route), 5 logic levels. Warning: 30.580MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "count_signal_inferred_clock" 691.563000 MHz ; 21 items scored, 15 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 1.286ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q KETA1/count_1 (from count_signal_inferred_clock +) Destination: FF Data in KETA1/count_3 (to count_signal_inferred_clock +) Delay: 2.654ns (31.6% logic, 68.4% route), 3 logic levels. Constraint Details: 2.654ns physical path delay KETA1/SLICE_31 to KETA1/SLICE_32 exceeds 1.445ns delay constraint less 0.077ns DIN_SET requirement (totaling 1.368ns) by 1.286ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.363 */SLICE_31.CLK to *1/SLICE_31.Q1 KETA1/SLICE_31 (from count_signal_inferred_clock) ROUTE 12 e 0.907 *1/SLICE_31.Q1 to SLICE_27.B0 display1_1 CTOF_DEL --- 0.238 SLICE_27.B0 to SLICE_27.F0 SLICE_27 ROUTE 3 e 0.907 SLICE_27.F0 to *1/SLICE_32.D1 seg7_118 CTOF_DEL --- 0.238 *1/SLICE_32.D1 to *1/SLICE_32.F1 KETA1/SLICE_32 ROUTE 1 e 0.001 *1/SLICE_32.F1 to */SLICE_32.DI1 KETA1/un1_count_1_i_m_i_3 (to count_signal_inferred_clock) -------- 2.654 (31.6% logic, 68.4% route), 3 logic levels. Warning: 366.166MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "carry3" 538.793000 MHz ; 56 items scored, 48 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 2.362ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q setnum1_0 (from CLK_c +) Destination: FF Data in KETA4/count_1__Q_res_reg (to carry3 +) Delay: 4.067ns (26.5% logic, 73.5% route), 4 logic levels. Constraint Details: 4.067ns physical path delay SLICE_36 to SLICE_45 exceeds 1.856ns delay constraint less 0.151ns M_SET requirement (totaling 1.705ns) by 2.362ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.363 SLICE_36.CLK to SLICE_36.Q0 SLICE_36 (from CLK_c) ROUTE 3 e 0.907 SLICE_36.Q0 to SLICE_46.A1 setnum1_0 CTOF_DEL --- 0.238 SLICE_46.A1 to SLICE_46.F1 SLICE_46 ROUTE 3 e 0.269 SLICE_46.F1 to SLICE_46.C0 I_57_t2 CTOF_DEL --- 0.238 SLICE_46.C0 to SLICE_46.F0 SLICE_46 ROUTE 11 e 0.907 SLICE_46.F0 to SLICE_25.A0 display4_0 CTOF_DEL --- 0.238 SLICE_25.A0 to SLICE_25.F0 SLICE_25 ROUTE 2 e 0.907 SLICE_25.F0 to SLICE_45.M0 KETA4/count_7_1 (to carry3) -------- 4.067 (26.5% logic, 73.5% route), 4 logic levels. Warning: 237.079MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "carry2" 441.112000 MHz ; 150 items scored, 133 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 3.735ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q setnum2_2 (from CLK_c +) Destination: FF Data in KETA3/count_3__Q_res_reg (to carry2 +) Delay: 5.850ns (22.5% logic, 77.5% route), 5 logic levels. Constraint Details: 5.850ns physical path delay SLICE_38 to SLICE_48 exceeds 2.266ns delay constraint less 0.151ns M_SET requirement (totaling 2.115ns) by 3.735ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.363 SLICE_38.CLK to SLICE_38.Q0 SLICE_38 (from CLK_c) ROUTE 4 e 0.907 SLICE_38.Q0 to SLICE_47.A1 setnum2_2 CTOF_DEL --- 0.238 SLICE_47.A1 to SLICE_47.F1 SLICE_47 ROUTE 5 e 0.907 SLICE_47.F1 to *3/SLICE_34.C1 I_59_t2 CTOF_DEL --- 0.238 *3/SLICE_34.C1 to *3/SLICE_34.F1 KETA3/SLICE_34 ROUTE 11 e 0.907 *3/SLICE_34.F1 to SLICE_29.C0 display3_2 CTOF_DEL --- 0.238 SLICE_29.C0 to SLICE_29.F0 SLICE_29 ROUTE 3 e 0.907 SLICE_29.F0 to SLICE_20.B0 KETA3/un7_count CTOF_DEL --- 0.238 SLICE_20.B0 to SLICE_20.F0 SLICE_20 ROUTE 2 e 0.907 SLICE_20.F0 to SLICE_48.M0 KETA3/un1_count_1_i_m_i_3 (to carry2) -------- 5.850 (22.5% logic, 77.5% route), 5 logic levels. Warning: 166.639MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "carry1" 441.112000 MHz ; 150 items scored, 135 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 3.735ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q swrite (from CLK_c +) Destination: FF Data in KETA2/count_0__Q_res_reg (to carry1 +) Delay: 5.850ns (22.5% logic, 77.5% route), 5 logic levels. Constraint Details: 5.850ns physical path delay SLICE_40 to KETA2/SLICE_12 exceeds 2.266ns delay constraint less 0.151ns M_SET requirement (totaling 2.115ns) by 3.735ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.363 SLICE_40.CLK to SLICE_40.Q0 SLICE_40 (from CLK_c) ROUTE 16 e 0.907 SLICE_40.Q0 to SLICE_47.B1 swrite CTOF_DEL --- 0.238 SLICE_47.B1 to SLICE_47.F1 SLICE_47 ROUTE 5 e 0.907 SLICE_47.F1 to *2/SLICE_33.C1 I_59_t2 CTOF_DEL --- 0.238 *2/SLICE_33.C1 to *2/SLICE_33.F1 KETA2/SLICE_33 ROUTE 12 e 0.907 *2/SLICE_33.F1 to *2/SLICE_28.C0 display2_2 CTOF_DEL --- 0.238 *2/SLICE_28.C0 to *2/SLICE_28.F0 KETA2/SLICE_28 ROUTE 3 e 0.907 *2/SLICE_28.F0 to *2/SLICE_11.A0 KETA2/un7_count CTOF_DEL --- 0.238 *2/SLICE_11.A0 to *2/SLICE_11.F0 KETA2/SLICE_11 ROUTE 2 e 0.907 *2/SLICE_11.F0 to *2/SLICE_12.M0 KETA2/un1_count_1_i_m_i_0 (to carry1) -------- 5.850 (22.5% logic, 77.5% route), 5 logic levels. Warning: 166.639MHz is the maximum frequency for this preference. Report Summary ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "CLK_c" 373.552000 MHz ; | 373.552 MHz| 30.580 MHz| 5 * | | | FREQUENCY NET | | | "count_signal_inferred_clock" | | | 691.563000 MHz ; | 691.563 MHz| 366.166 MHz| 3 * | | | FREQUENCY NET "carry3" 538.793000 MHz ; | 538.793 MHz| 237.079 MHz| 4 * | | | FREQUENCY NET "carry2" 441.112000 MHz ; | 441.112 MHz| 166.639 MHz| 5 * | | | FREQUENCY NET "carry1" 441.112000 MHz ; | 441.112 MHz| 166.639 MHz| 5 * | | | ---------------------------------------------------------------------------- 5 preferences(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- un6_timer | 8| 160| 17.11% | | | swrite | 16| 157| 16.79% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 5 clocks: Clock Domain: CLK_c Source: CLK.PAD Loads: 47 Covered under: FREQUENCY NET "CLK_c" 373.552000 MHz ; Data transfers from: Clock Domain: count_signal_inferred_clock Source: SLICE_30.Q0 Covered under: FREQUENCY NET "CLK_c" 373.552000 MHz ; Transfers: 4 Clock Domain: carry3 Source: SLICE_29.Q0 Covered under: FREQUENCY NET "CLK_c" 373.552000 MHz ; Transfers: 6 Clock Domain: carry2 Source: KETA2/SLICE_28.Q0 Covered under: FREQUENCY NET "CLK_c" 373.552000 MHz ; Transfers: 7 Clock Domain: carry1 Source: SLICE_27.Q0 Covered under: FREQUENCY NET "CLK_c" 373.552000 MHz ; Transfers: 7 Clock Domain: count_signal_inferred_clock Source: SLICE_30.Q0 Loads: 3 Covered under: FREQUENCY NET "count_signal_inferred_clock" 691.563000 MHz ; Clock Domain: carry3 Source: SLICE_29.Q0 Loads: 5 Covered under: FREQUENCY NET "carry3" 538.793000 MHz ; Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY NET "carry3" 538.793000 MHz ; Transfers: 3 Clock Domain: carry2 Source: KETA2/SLICE_28.Q0 Loads: 8 Covered under: FREQUENCY NET "carry2" 441.112000 MHz ; Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY NET "carry2" 441.112000 MHz ; Transfers: 4 Clock Domain: carry1 Source: SLICE_27.Q0 Loads: 8 Covered under: FREQUENCY NET "carry1" 441.112000 MHz ; Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY NET "carry1" 441.112000 MHz ; Transfers: 4 Timing summary: Timing errors: 935 Score: 3840197 Cumulative negative slack: 3840197 Constraints cover 1106 paths, 5 nets, and 513 connections (84.2% coverage) -------------------------------------------------------------------------------- Generated from the file 'C:\Documents and Settings\rerofumi\My Documents\pld_develop\ramen_timer_lattice\ramen_timer.tw1'