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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:42:12 06/28/2006 
-- Design Name: 
-- Module Name:    led_control - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led_control is
    Port ( led : out  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC);
end led_control;

architecture Behavioral of led_control is
--	signal      led_pattern : std_logic_vector(7 downto 0):= "00010100";
	signal		waitloop : std_logic_vector(23 downto 0) := "000000000000000000000000";
	signal		flag : std_logic := '0';

begin
  led_display: process(clk)
  begin
    if clk'event and clk='1' then
	   waitloop <= waitloop + '1';
		if waitloop = "111111111111111111111111" then
         if flag = '0' then
				flag <= '1';
				led <= "00101010";
			else
				flag <= '0';
				led <= "00010100";
			end if;
			waitloop <= "000000000000000000000000";
		end if;
    end if;
  end process led_display;
 

end Behavioral;